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TDA7411
ADVANCED CAR SIGNAL PROCESSOR
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FULLY INTEGRATED SIGNAL PROCESSOR OPTIMIZED FOR CAR RADIO APPLICATIONS FULY PROGRAMMABLE BY I2C BUS INCLUDES AUDIOPROCESSOR, STEREODECODER WITH NOISE BLAMKER AND MULTIPATH DETECTOR SOFTMUTE FUNCTION PROGRAMMABLE ROLL-OFF COMPENSATION NO EXTERNAL COMPONENTS
s s
s s s
TQFP44 ORDERING NUMBER: TDA7411
DESCRIPTION The TDA7411 is the successor of the TDA7407 in the CSP family introduced by the TDA7460/61. It uses the same innovative concepts and design technologies allowing fully software programmability through I2C bus and overall cost optimization for the system designer. The device includes a three band audio processor with extended configurable input and output stagBLOCK DIAGRAM es and absence of external components for filter settings, a last generation stereo decoder with multi path detector and a sophisticated stereo blend, high cut control and noise cancellation circuitry. Strength points of the CSP approach are flexibility and overall cost/room saving in the application, combined with high performances.
October 2003
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ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Range Operating Storage Temperature Range Parameter Value 10.5 -40 to 85 -55 to 150 Unit V C C
SUPPLY
Symbol VS IS SVRR Parameter Supply Voltage Supply Current Ripple Rejection @ 1KHz VS = 9V Audioprocessor (all filters flat) Stereodecoder + Audioprocessor Test Condition Min. 7.5 Typ. 8 45 60 55 Max. 10 Unit V mA dB dB
ESD All pins are protected against ESD according to the MIL883 standard. PIN CONNECTION (Top view)
ACoutR ACin0R
34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22
ACoutL
36
44
43
42
41
40
39
38
37
AUXL AUXC AUXR CDCHR+ CDCHRCDCHLCDCHL+ NV+ NVAM MPX
ACin0L
35
SubR
SubL
MDR
CDR
MDL
CDL
Cref
1 2 3 4 5 6 7 8 9 10 11
ACin1R ACin1L ACin2L ACin2R ACin3R ACin3L VS GND OutLF OutRF OutRR
AFS
Mpin
MPout
Qual
Mute
SDA
SCL
FreeR
FreeL
OutLR
Level
PINCON-TDA7411
THERMAL DATA
Symbol Rth-j pins Parameter Thermal Resistance Junction to pins Max Value 85 Unit C/W
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PIN DESCRIPTION
Nr. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name AUXL AUXC AUXR CDCHR+ CDCHRCDCHLCDCHL+ NV+ NVAM MPX Level MPin MPout Qual AFS Mute SDA SCL FreeR FreeL OutLR OutRR OutRF OutLF GND VS ACin3L ACin3R ACin2R ACin2L ACin1L ACin1R ACin0R ACin0L ACoutL ACoutR SubR SubL Cref MDL MDR CDR CDL Quasi Differential Input Left Quasi Differential Input Common Quasi Differential Input Right Full Differential Input Right Plus Full Differential Input Right Minus (not used in quasi differential mode) Full Differential Input Left Minus (CDCHCom in Qdiff mode) Full Differential Input Left Plus Mono Differential Input Plus Mono Differential Input Minus AM Input FM Stereo Decoder Input Level Input Stereo Decoder Multi Path Input Multi Path Output Stereo Decoder Quality Output Alternative Frequency Search Drive Soft Mute Drive I2C Data Line I2C Clock Line Free Right Speaker Output Free Left Speaker Output Rear Left Speaker Output Rear Right Speaker Output Front Right Speaker Output Front Left Speaker Output Supply Ground Supply Voltage Pre-speaker Input Three Left Pre-speaker Input Three Right Pre-speaker Input Two Right Pre-speaker Input Two Left Pre-speaker Input Three Left Pre-speaker Input Three Right Pre-speaker Input Zero Right Pre-speaker Input Zero Left Pre-speaker Output Left Pre-speaker Output Right Sub Channel Selector Output Right Sub Channel Selector Output Left Reference Capacitor Pin Mini Disk Input Left Mini Disk Input Right Compact Disk Input Right (Test mode Output) Compact Disk Input Left Function Type I I I I I I I I I I I I I O O I I I/O I O O O O O O S S I I I I I I I I O O O O O I I I I
Pin type legenda: I = Input ; O = Output; I/O = Input/Output; S = Supply; nc = not connected.
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AUDIO PROCESSOR PART Input Multiplexer - - - - - - - full differential stereo input configurable as quasi-differential input quasi differential auxiliary stereo input mini disk stereo input configurable as mono differential input compact disk stereo input mono differential navigation input AM mono input second multiplexer for sub channel output
Volume control - 1dB attenuator - Max. gain 15dB - Max. attenuation 79dB Bass Control - - - - 2nd order frequency response Center frequency programmable in 4(5) steps DC gain programmable 15 x 1dB steps
Mid Control - - - - 2nd order frequency response Center frequency programmable in 4 steps Q-factor programmable in 2 steps 15 x 1dB steps
Treble Control - 2nd order frequency response - Center frequency programmable in 4 steps - 15 x 1dB steps Speaker Control - - - - - 6 independent speaker controls in 1dB steps max. gain 15dB max. attenuation 79dB implemented soft mute capability speaker input multiplexer
Mute Functions - independent direct fast mute controlled by I2C interface - independent soft mute for Front L/R, Rear and Free controlled by I2C interface - digitally controlled soft mute with 4 programmable mute-times - pin controlled soft mute soft mute monitor function @ Mute pin
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ELECTRICAL CHARACTERISTICS (VS = 8V; Tamb = 25C; RL = 10K; all gains = 0dB; f = 1KHz; unless otherwise specified)
Symbol INPUT SELECTOR Rin VCL SIN GIN MIN GIN MAX GSTEP VDC Input Resistance Clipping Level Input Separation Min. Input Gain Max. Input Gain Step Resolution DC Steps Adjacent Gain Step GMIN to GMAX FULL AND QUASI DIFFERENTIAL STEREO INPUT Rin CMRR eN Rin CMRR Input Resistance (see Figure 1) Common Mode Rejection Ratio Differential Common Mode VCM = 1VRMS @ 1KHz VCM = 1VRMS @ 10KHz Output Noise @ Speaker Outputs 20Hz to 20KHz flat; all stages 0dB Input Resistance Common Mode Rejection Ratio Differential VCM = 1VRMS @ 1KHz VCM = 1VRMS @ 10KHz VOLUME CONTROL GMAX AMAX ASTEP EA ET VDC Max Gain Max Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps Adjacent Attenuation Steps From 0dB to GMIN SOFT MUTE/AFS AMUTE TD Mute Attenuation Delay Time T1 T2 T3 T4 VTH low VTH high VTH high VSMon RPD CRANGE ASTEP Low Threshold for Mute/AFS-Pin High Threshold for SM -Pin High Threshold for AFS -Pin Monitor Voltage for SMon Internal Pull-up Resistor Control Range Step Resolution 13 0.5
1
Parameter
Test Condition all inputs except Phone THD < 0.3%
Min. 70 1.6 80 -0.5 14 0.5 -5 -10 70 70 45 45
Typ. 100 1.7 100 0 15 1 0.5 5 100 100 70 60 9
Max. 130
Unit K VRMS dB
0.5 16 1.5 5 10 130 130
dB dB dB mV mV K K dB dB
15
V K dB dB
MONO DIFFERENTIAL INPUT (NV and MD in differential mode) 40 40 40 14 74 0.5 G = -20 to +20dB G = -60 to +20dB -1.25 -4 56 70 60 15 79 1 0 0 0.1 0.5 80 100 0.24 0.48 10.1 20.2 1 1.8 2.4 2.4 100 15 1 17 1.5 1.5 +1.25 +3 2 3 5 16
dB dB dB dB dB dB mV mV dB ms ms ms ms V V V V K dB dB
BASS CONTROL
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ELECTRICAL CHARACTERISTICS (continued) (VS = 8V; Tamb = 25C; RL = 10K; all gains = 0dB; f = 1KHz; unless otherwise specified)
Symbol fC Parameter Center Frequency fC1 fC2 fC3 fC4 QBASS Quality Factor Q1 Q2 Q3 Q4 DCGAIN Bass-DC-Gain DC = off DC = on MID CONTROL CRANGE ASTEP fC Control Range Step Resolution Center Frequency fC1 fC2 fC3 fC4 QBASS Quality Factor Q1 Q2 TREBLE CONTROL GMAX ASTEP fC Control Range Step Resolution Center Frequency fC1 fC2 fC3 fC4 SPEAKER ATTENUATORS Rin Rin Impedance @ACin0,2,3 Impedance @ACin1 Rin1 Rin2 Rin3 GMAX AMAX ASTEP AMUTE EE VDC VCLIP RL CL Max. Gain Max. Attenuation Step Resolution Output Mute Attenuation Attenuation Set Error DC Steps Clipping Level Output Load Resistance Output Load Capacitance Adjacent Attenuation Steps d = 0.3% -5 1.6 2 10 0.1 1.8 35 35 28 21 13 -74 0.5 80 50 50 40 30 15 -79 1 90 2 5 1.5 65 65 52 39 17 k k k k dB dB dB dB dB mV VRMS k nF 13 0.5 8 10 12 14 15 1 10 12.5 15 17.5 17 1.5 12 15 18 21 dB dB KHz KHz KHz KHz 13 0.5 450 0.9 1.35 1.8 0.9 1.8 15 1 500 1 1.5 2 1 2 17 1.5 550 1.1 1.65 2.2 1.1 2.2 dB dB Hz kHz kHz kHz Test Condition Min. 54 63 72 90 0.9 1.1 1.3 1.8 -1 3.5 Typ. 60 70 80 100 (150)(2) 1 1.25 1.5 2 0 4.4 Max. 66 77 88 110 1.1 1.4 1.7 2.2 1 5.5 dB dB Unit Hz Hz Hz Hz
AUDIO OUTPUTS
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ELECTRICAL CHARACTERISTICS (continued) (VS = 8V; Tamb = 25C; RL = 10K; all gains = 0dB; f = 1KHz; unless otherwise specified)
Symbol ROUT VDC eNO Parameter Output Impedance DC Voltage Level Output Noise BW = 20Hz - 20kHz output muted all gains = 0dB S/N Signal to Noise Ratio all gains = 0dB;flat; VO = 2VRMS bass, treble at +12dB; a-weighted; VO = 2.6VRMS d Distortion all stages 0dB Mono Diff Inputs, Vout = 0.75VRMS All other inputs, Vout = 1VRMS VOUT=1VRMS ; Bass & Treble = 12dB SC ET VPOR VIL VIH IIN VO Channel Separation L/R Total Tracking Error Internal POR Voltage Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge VIN = 0.4V VO = 1.6mA 2.5 -5 5 0.4 AV = 0 to -20dB AV = -20 to -60dB BUS INPUTS 0.8 V V A V 80 -1 -2 102 96 3 6.5 6.5 110 100 0.04 0.1 10 15 V V V dB dB % 3.8 Test Condition Min. Typ. 30 4 Max. 120 4.2 Unit V
GENERAL
0.05 100 0 0 3
0.15 1 2
% dB dB dB V
1) The SM and AFS pin are active low (Mute = 0) 2) See description of Audio processor Part section 1.8.
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DESCRIPTION OF THE AUDIOPROCESSOR PART Input Multiplexer - CDCH full differential input configurable as quasi-differential input - auxiliary quasi-differential input - CD stereo - MD stereo configurable as mono-differential phone input - mono-differential NV input - AM mono - and stereo decoder input. Figure 1. Input Selectors TDA7411
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Input stages In the basic configuration one full differential, one quasi-differential, two single ended stereo, one monodifferential and two tuner (AM and MPX) inputs are available. In addition the ac coupling input Acin0 can be used as single ended input for the input multiplexer. The full-differential input can be switched into quasi-differential mode (see Fig. 2) and the MD single ended input can be used as mono-differential input (see Fig.1). Figure 2. Full differential input
AutoZero In order to reduce the number of pins there is no AC coupling between the In-Gain and the following stage, so that any offset generated by or before the In-Gain-stage would be transferred or even amplified to the output. To avoid that effect a special Offset-cancellation-stage called AutoZero is implemented. This stage is located after the In-Gain-stage to eliminate all offsets generated by the stereo decoder, the Input-Stages and the In-Gain (Please notice that externally generated offsets, e.g. generated through the leakage current of the coupling capacitors, are not canceled). The auto-zeroing is started every time the DATA-BYTE 0 is selected and takes a time of max. 0.3ms. To avoid audible clicks the audio processor is muted before the tone control stage during this time. AutoZero-Remain In some cases, for example if the P is executing a refresh cycle of the IIC-Bus-programming, it is not useful to start a new AutoZero action because no new source is selected and an undesired mute would appear at the outputs. For such applications the TDA7411 could be switched in the AutoZero-RemainMode (Bit 6 of the sub address byte). If this bit is set to high, the DATABYTE 0 could be loaded without invoking the AutoZero and the old adjustment-value remains. Sub Channel Multiplexer All input stages are available as source in the sub channel multiplexer. The selected source is buffered and available at the pins SubR, SubL.
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Mute Capability of Audio Processor The main channel and the sub channel of the TDA7411 can be muted after the Source selectors. This mute (no soft mute!) must be started by I2C bus. The digitally controlled SoftMute stages are placed in the speaker and allow muting/demuting of the signal with an I2C-bus programmable slope. The mute process can either be activated by the SoftMute pin or by the I2C-bus. The slope is realized in a special S-shaped curve to mute slowly in the critical regions (see Figure 3). Figure 3. Soft mute-Timing
Note: Please notice that a started Mute-action is always terminated and could not be interrupted by a change of the mute -signal. Using the IIC bus control the soft mute can be activated independently for FrontL, FrontR, Rear and Free. For timing purposes the Bit 3 of the I2C-bus output register is set to 1 as soon as the soft mute of any speaker is started until the end of demuting of all speakers. The Mute pin is able to work as monitor for the same signal. The standard function of the pin is not influenced by the monitor function.
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Bass There are four parameters programmable in the bass stage: Attenuation Figure 4 shows the attenuation as a function of frequency at a center frequency of 80Hz. Figure 4. Bass Control @ fC = 80Hz, Q = 1
15.0
10.0
5.0
0.0
-5.0
10.0
15.0 10.0
100. 0
1. 0K
10.0 K
Center Frequency Figure 5 shows the four possible center frequencies 60, 70, 80 and 100Hz. Figure 5.
15. 0
12. 5
10. 0
7. 5
5. 0
2. 5
0. 0 10.0 100. 0 1. 0K 10.0K
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Quality Factors Figure 6 shows the four possible quality factors 1, 1.25, 1.5 and 2. Figure 6. Bass Quality factors @ Gain = 14dB, fC = 80Hz
15. 0
12. 5
10. 0
7. 5
5. 0
2. 5
0. 0
10. 0
100. 0
1. 0K
10.0K
DC Mode In this mode the DC-gain is increased by 5.1dB. In addition the programmed center frequency and quality factor is decreased by 25%, which can be used to reach alternative center frequencies or quality factors. Figure 7. Bass normal and DC Mode @ Gain = 14dB, fC = 80Hz
15. 0
12. 5
10. 0
7. 5
5. 0
2. 5
0. 0 10. 0 100. 0 1. 0K 10. 0K
Note: In general the center frequency, Q and DC-mode can be set independently. The exception from this rule is the mode (5/xx1111xx) where the center frequency is set to 150Hz instead of 100Hz.
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MID There are 3 parameters programmable in the mid stage: Attenuation Figure 8 shows the attenuation as a function of frequency at a center frequency of 1kHz. Figure 8. Mid Control @ fC = 1kHz, Q = 1
15. 0
10. 0
5. 0 0. 0 5. 0 -10. 0
-15. 0 10. 0 100. 0 1. 0K 10.0K
Center Frequency Figure 9 shows the four possible center frequencies 500Hz, 1kHz, 1.5kHz and 2kHz. Figure 9.
15. 0
12. 5
10. 0
7. 5 5. 0 2. 5 0. 0 10.0 100. 0 1. 0K 10. 0K
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Quality Factor Figure 10 shows the two possible quality factors 1 and 2 at a center frequency of 1kHz. Figure 10. Mid Q-factor @ fC = 1kHz, Gain=14dB
15. 0
12. 5
10. 0
7. 5 5. 0 2. 5 0. 0 10.0 100. 0 1. 0K 10. 0K
TREBLE There are two parameters programmable in the treble stage: Attenuation Figure 11 shows the attenuation as a function of frequency at a center frequency of 17.5kHz. Figure 11. Treble Control @ fC = 17.5kHz
15.0
10.0
5.0
0.0
-50 .
10.0
-15.0 10. 0 100.0 1.0K 10.0K
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Center Frequency Figure 12 shows the four possible center frequencies 10k, 12.5k, 15k and 17.5kHz. Figure 12. Treble Center Frequencies @ Gain = 14dB
15. 0
12. 5
10. 0
7. 5
5. 0
2. 5
0. 0
10. 0
100. 0
1. 0K
10. 0K
Speaker Coupling In some applications additional signal manipulations are desired, for example surround-sound or moreband-equalizing. For this purpose an AC-Coupling with four different AC-Coupling inputs is placed before the speaker-attenuators. The input-impedance of the AC-Inputs is always 50k with exception of AC input ACin1, which has programmable input impedance. For ACin3 exists an internal mixing stage and an internal mono low pass filter, which is available as input only for the speaker FreeL/R. There are two possibilities for internal DC Coupling: - main channel after the bass filter - main channel after the middle filter (same as at ACout pin) The I2C bus programming tables shows the possible speaker sources.
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Low Pass Filter Figure 13 shows the five possible corner frequencies of the low pass filter: Figure 13. Low Pass Corner Frequencies
0 -3 dB -10
-20
-30
-40 10 100 Hz 100 0
Anti-Radiation-Filter An Anti-Radiation-Filter is implemented to suppress the radiation at the SC-clock-frequency and its harmonics. This radiation is only present if the stereo decoder is selected and/or SC-Filters are active (<>0dB). If not, the filter can be switched off in order to optimize the noise-performance. Speaker Attenuator The speaker-attenuators have exactly the same control range like the Volume-stage. Every stereo speaker stage has an implemented independently I2C controlled and Mute pin controlled SoftMute stage (see section mute capability of AP).
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STEREODECODER PART Features: - no external components necessary - PLL with adjustment free, fully integrated VCO - automatic pilot dependent MONO/STEREO switching - very high suppression of intermodulation and interference - programmable Roll-Off compensation - dedicated RDS-Soft mute - High cut- and Stereo blend-characteristics programmable in a wide range - internal Noise blanker with several threshold controls - alternative frequency search function - Multipath-detector with programmable internal/external influence - I2C-bus control of all necessary functions . ELECTRICAL CHARACTERISTICS (VS = 8V; deemphasis time constant = 50s,VMPX = 500mV(75KHz deviation), fm= 1KHz, Gv = 6dB, Tamb = 27C; unless otherwise specified)
Symbol Vin Rin GMIN GMAX GSTEP SVRR THD S+N -------------N VPTHST1 VPTHST0 Parameter MPX Input Level Input Resistance Min. Input Gain Max. Input Gain Step Resolution Supply Voltage Ripple Rejection Max. channel Separation Total Harmonic Distortion Signal plus Noise to Noise Ratio A-weighted, S = 2VRMS 80 Vripple = 100mV; f = 1KHz Test Condition Gv = 3.5dB 70 1.5 8.5 1.75 35 30 Min. Typ. 0.5 100 3.5 11 2.5 60 50 0.02 91 0.3 Max. 1.25 130 4.5 12.5 3.25 Unit VRMS K dB dB dB dB dB % dB
MONO/STEREO-SWITCH Pilot Threshold Voltage Pilot Threshold Voltage for Stereo, PTH = 1 for Stereo, PTH = 0 for Mono, PTH = 1 for Mono, PTH = 1 10 15 7 10 0.5 Bit 7, Subadr, 10 = 0, VLEVEL >> VHCH Bit 7, Subadr, 10 = 1, VLEVEL >> VHCH Bit 7, Subadr, 10 = 0, VLEVEL >> VHCL Bit 7, Subadr, 10 = 1, VLEVEL >> VHCL 25 50 100 150 50 75 150 225 75 100 200 300 15 25 12 19 25 35 17 25 mV mV mV mV % s s s s
VPTHMO1 Pilot Threshold Voltage VPTHMO0 Pilot Threshold Voltage PLL f/f tHC50 tHC75 tHC50 tHC75 Capture Range Deemphasis Time Constant Deemphasis Time Constant Highcut Time Constant Highcut Time Constant DEEMPHASIS and HIGHCUT
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ELECTRICAL CHARACTERISTICS (continued) (VS = 8V; deemphasis time constant = 50s,VMPX = 500mV(75KHz deviation), fm= 1KHz, Gv = 6dB, Tamb = 27C; unless otherwise specified)
Symbol REF5V TCREF5V LGmin LGmax LGstep Parameter Internal Reference Voltage Temperature Coefficient Min. LEVEL Gain Max. LEVEL Gain LEVEL Gain Step Resolution -1 8 0.3 25 54 2.2 38 62 5 12 28 2.2 40 Test Condition Min. 4.7 Typ. 5 3300 0 10 0.67 29 58 4.2 42 66 8.4 17 33 4.2 50 75 62 90 65 75 70 75 95 84 1 12 1 33 62 6.2 46 70 12 22 38 6.2 Max. 5.3 Unit V ppm dB dB dB %REF5V %REF5V %REF5V %REF5V %REF5V %REF5V %VHCH %VHCH %VHCH dB dB dB dB dB dB dB dB dB dB STEREOBLEND-and HIGHCUT-CONTROL
VSBLmin Min. Voltage for Mono VSBLmax Min. Voltage for Mono VSBLstep Step Resolution VHCHmin Min. Voltage for NO Highcut VHCHmax Min. Voltage for NO Highcut VHCHstep Step Resolution VHCLmin Min. Voltage for FULL Highcut VHCLmax Max. Voltage for FULL Highcut VHCLstep Step Resolution Carrier and harmonic suppression at the output 19 38 57 76 2 3 57 67 114 190 Pilot Signal f = 19KHz Subcarrier f = 38KHz Subcarrier f = 57KHz Subcarrier f = 76KHz fmod = 10KHz, fspur = 1KHz fmod = 13KHz, fspur = 1KHz Signal f = 57KHz Signal f = 67KHz Signal f = 114KHz Signal f = 190KHz
Intermodulation (Note 1)
Traffic Ratio (Note 2) SCA - Subsidiary Communications Authoorization (Note 3) ACI - Adjacent Channel Interference (Note 4)
Notes to the characteristics: 1. Intermodulation Suppression: V O ( sig na l ) ( at1 kHz ) 2 = ----------------------------------------------------- ; fs = (2 x 10kHz) - 19kHz V O ( s pu rious ) ( a t1kHz ) V O ( sig na l ) ( at1 kHz ) 3 = ----------------------------------------------------- ; fs = (3 x 13kHz) - 38kHz V O ( s pu rious ) ( a t1kHz ) measured with: 91% pilot signal; fm = 10kHz or 13kHz. 2. Traffic Radio (V.F.) Suppression: measured with: 91% stereo signal; 9% pilot signal; fm=1kHz; 5% sub-
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carrier (f = 57kHz, fm = 23Hz AM, m = 60%) V O ( sig nal ) ( at1 kHz ) 57 ( V.W > F. ) = ------------------------------------------------------------------------V O ( sp uriou s ) ( at1k Hz 23k Hz ) 3. SCA ( Subsidiary Communications Authorization ) measured with: 81% mono signal; 9% pilot signal; fm = 1kHz; 10%SCA - subcarrier ( fs = 67kHz, unmodulated ). V O ( si gna l ) ( at1 kHz ) 67 = ----------------------------------------------------- ; Fs =(2 x 38kHz) - 67kHz V O ( spu riou s ) ( a t9k Hz ) 4. ACI ( Adjacent Channel Interference ): V O ( s igna l ) ( a t1kHz ) 114 = ----------------------------------------------------- ; Fs = 110kHz - (3 x 38kHz) V O ( sp uriou s ) ( at4k Hz ) V O ( s igna l ) ( a t1kHz ) 114 = ----------------------------------------------------- ; Fs = 186kHz - (5 x 38kHz) V O ( sp uriou s ) ( at4k Hz ) measured with: 90% mono signal; 9% pilot signal; fm =1kHz; 1% spurious signal( fs = 110kHz or 186kHz, unmodulated). NOISE BLANKER PART Features: - internal 2nd order 140kHz high-pass filter - programmable trigger threshold - trigger threshold dependent on high frequency noise with programmable gain - additional circuits for deviation- and fieldstrength-dependent trigger adjustment - very low offset current during hold time due to opamps with MOS inputs - 4 selectable pulse suppression times - programmable noise rectifier charge/discharge current ELECTRICAL CHARACTERISTICS (continued)
Symbol VTR Parameter Trigger Threshold
0) 1)
Test Condition meas. with VPEAK = 0.9V NBT = 111 NBT = 110 NBT = 101 NBT = 100 NBT = 011 NBT = 010 NBT = 001 NBT = 000
Min. (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) 0.5 1.5
Typ. 30 35 40 45 50 55 60 65 260 220 180 140 0.9 1.7 3.5
Max. (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) (c) 1.3 2.1
Unit mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP mVOP V V V
VTRNOISE Noise Controlled Trigger Threshold 2)
meas. with VPEAK = 1.5V
NCT = 00 NCT = 01 NCT = 10 NCT = 11
VRECT
Rectifier Voltage
VMPX = 0mV VMPX = 50mV; f = 150KHz VMPX = 200mV; f = 150KHz
NRD 6) = 00
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ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition means. with VMPX = 500mV (75KHz dev.) OVD = 11 OVD = 10 OVD = 01 OVD = 00 VRECT FS Fieldstrength Controlled Rectifier Voltage 4) means. with VMPX = 0mV VLEVEL << VSBL (fully mono) Signal HOLDNin Testmode FSC = 11 FSC = 10 FSC = 01 FSC = 00 TS Suppression Pulse Duration 5) BLT = 00 BLT = 10 BLT = 01 BLT = 00 VRECTADJ Noise Rectifier discharge adjustment 6) Signal PEAK in Testmode NRD = 00
6)
Min. 0.5 0.9 1.7 2.5 0.5 0.9 1.7 2.1
Typ. 0.9(off) 1.2 2.0 2.8 0.9(off) 1.4 1.9 2.4 38 32 25.5 22
Max. 1.3 1.5 2.3 3.1 1.3 1.5 2.3 3.1
Unit VOP VOP VOP VOP V V V V s s s s
VRECT DEV deviation dependent rectifier Voltage 3)
(c) (c) (c) (c) (c) (c) (c) (c) (c) (c)
0.3 0.8 1.3 2.0 10 20 0.3 0.5 0.7 0.9
(c) (c) (c) (c) (c) (c) (c) (c) (c) (c)
V/ms V/ms V/ms V/ms mV/s mV/s V/ms V/ms V/ms V/ms
NRD = 01 6) NRD = 10 6) NRD = 11 6)
SRPEAK
Noise Rectifier Charge
Signal PEAK in Testmode
PCH = 0 7) PCH = 1 7)
VADJMP
Noise Rectifier adjustment through Multipath 8)
Signal PEAK in Testmode
MPNB = 00 8) MPNB = 01 8) MPNB = 10 8) MPNB = 11 8)
(c) = by design/characterization functionally guaranteed through dedicated test mode structure 0) All Thresholds are measured using a pulse with TR =2s, THIGH = 2s and TF = 10s. The repetition rate must not increase the PEAK voltage.
Figure 14. Timing
VIN VOP
DC
D97AU636
TR
THIGH
TF
Time
1) NBT represents the Noiseblanker Byte bits D2, D0 for the noise blanker trigger threshold 2) NAT represents the Noiseblanker Byte bit pair D 4, D3 for the noise controlled triggeradjustment 3) OVD represents the Noiseblanker Byte bit pair D7, D6 for the over deviation detector 4) FSC represents the Fieldstrength Byte bit pair D1, D0 for the fieldstrength control 5) BLT represents the Speaker RR Byte bit pair D7, D6 for the blanktime adjustment 6) NRD represents the Configuration-Byte bit pair D1, D0 for the noise rectifier discharge-adjustment 7) PCH represents the Stereodecoder-Byte bit D5 for the noise rectifier charge-current adjustment 8) MPNB represents the HighCut-Byte bit D7 and the Fieldstrength-Byte D 7 for the noise rectifier multipath adjustment
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Figure 15. Trigger Threshold vs. VPEAK
VTH
260mV(00) 220mV(01) 180mV(10) 140mV(11) MIN. TRIG. THRESHOLD NOISE CONTROLLED TRIG. THRESHOLD 65mV 8 STEPS 30mV VPEAK(V)
0.9V
D97AU648
1.5V
Figure 16. Deviation Controlled Trigger Adjustment
VPEAK (VOP) 00
2.8 2.0
01
10 1.2 0.9 DETECTOR OFF (11)
D97AU649
20
32.5
45
75
DEVIATION(KHz)
Figure 17. Field strength Controlled Trigger Adjustment
VPEAK MONO STEREO
3V
2.4V(00) 1.9V(01) 1.4V(10) NOISE ATC_SB OFF (11)
0.9V
noisy signal
D97AU650
good signal
E'
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MULTIPATH DETECTOR Features: - internal 19kHz band-pass filter - programmable band-pass and rectifier gain - two pin solution fully independent usable for external programming - selectable internal influence on Stereoblend ELECTRICAL CHARACTERISTICS (continued)
Symbol fCMP GBPMP Parameter Center frequency of MultipathBandpass Band pass Gain Test Condition stereo decoder locked on Pilot tone bits D2, D1 configuration byte = 00 bits D2, D1 configuration byte = 01 bits D2, D1 configuration byte = 10 bits D2, D1 configuration byte = 11 GRECTMP Rectifier Gain bits D7, D6 configuration byte = 00 bits D7, D6 configuration byte = 01 bits D7, D6 configuration byte = 10 bits D7, D6 configuration byte = 11 ICHMP IDISMP Rectifier Charge Current bit D5, configuration byte = 0 bit D5, configuration byte = 1 0.5 Min. Typ. 19 6 12 16 18 7.6 4.6 0 off 0.2 0.4 1 1.5 A Max. Unit kHz dB dB dB dB dB dB dB
Rectifier Discharge Current
mA
QUALITY DETECTOR ELECTRICAL CHARACTERISTICS (continued)
Symbol A Parameter Multipath Influence Factor Test Conditions Addr12 / Bit 5+6 00 01 10 11 00 01 10 11 Min. Typ. 0.2 0.3 0.4 0.5 15 12 9 6 Max. Unit dB dB dB dB dB dB dB dB
A
Noise Influence Factor
Addr16 / Bit 1+2
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FUNCTIONAL DESCRIPTION OF STERO DECODER Figure 18. Block diagram of the stereo decoder
The stereo decoder-part of the TDA7411 (see Fig. 18) contains all functions necessary to demodulate the MPX-signal like pilot tone-dependent MONO/STEREO-switching as well as "stereoblend" and "highcut". Adaptations like programmable input gain, roll-off compensation, selectable deemphasis time constant and a programmable field strength input allow using different IF-devices. InGain + Infilter The InGain stage allows adjusting the MPX-signal to a magnitude of about 1Vrms internally, which is the recommended value. The 4.th order input filter has a corner frequency of 80kHz and is used to attenuate spikes and noise and acts as an anti-aliasing filter for the following switch capacitor filters. Demodulator In the demodulator block the left and the right channel are separated from the MPX-signal. In this stage also the 19-kHz pilot tone is canceled. For reaching a high channel separation the TDA7411 offers an I2Cbus programmable roll-off adjustment, which is able to compensate the low pass behavior of the tuner section. If the tuner's attenuation at 38kHz is in a range from 13.8% to 24.6% the A673 needs no external network in front of the MPX-pin. Within this range an adjustment to obtain at least 40dB channel separation is possible. The bits for this adjustment are located together with the field strength adjustment in one byte. This gives the possibility to perform an optimization step during the production of the car radio where the channel separation and the field strength control are trimmed. The setup of the stereoblend characteristics, which is programmable in a wide range. Deemphasis and Highcut The deemphasis low pass allows to choose between a time constant of 50s and 75s (bit D7, stereo decoder byte). The highcut control range will be in both cases HC = 2x Deemp. Inside the highcut control range (between VHCH and VHCL) the LEVEL signal is converted into a 5-bit word, which controls the low pass time constant between Deemp...3x Deemp. Thereby the resolution will remain always 5 bits indepen-
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dently of the absolute voltage range between the VHCH- and VHCL-values. The highcut function can be switched off by I2C-bus (bit D7, Field strength byte set to "0"). The setup of the highcut characteristics is described in 2.9. PLL and Pilot tone-Detector The PLL has the task to lock on the 19kHz pilot tone during a stereo-transmission to allow a correct demodulation. The included pilot tone-detector enables the demodulation if the pilot tone reaches the selected pilot tone threshold VPTHST. Two different thresholds are available. By reading the status byte of the A673 via I2C-bus the detector output (signal STEREO, see block diagram) can be checked. Field Strength Control The field strength input is used to control the highcut- and the stereoblend-function. In addition the signal can be also used to control the noise blanker thresholds and as input for the multipath detector. LEVEL-Input and -Gain To suppress undesired high frequency modulation on the highcut- and stereoblend-function the LEVEL signal is low pass filtered firstly. The filter is a combination of a 1.st-order RC-low pass at 53kHz (working as anti-aliasing filter) and a 1.st-order switched capacitor low pass at 2.2kHz. The second stage is a programmable gain stage to adapt the LEVEL signal internally to different IF-devices (see test mode section 5: LEVELINTERN). The gain is widely programmable in 16 steps from 0dB to 10dB (step=0.67dB). These 4 bits are located together with the Roll-Off bits in the "Stereo decoder-Adjustment"-byte to simplify a possible adaptation during the production of the car radio. Stereoblend Control The stereoblend control block converts the internal LEVEL-voltage (LEVELINTERN) into a demodulator compatible analog signal, which is used to control the channel separation between 0dB and the maximum separation. Internally this control range has a fixed upper limit, which is the internal reference voltage REF5V. The lower limit can be programmed between 29.2 and 58% of REF5V in 4.167% steps (see figs.19, 20). To adjust the external LEVEL-voltage to the internal range two values must be defined: the LEVEL gain LG and VSBL (see fig. 20). To adjust the voltage where the full channel separation is reached (VST) the LEVEL gain LG has to be defined. The following equation can be used to estimate the gain: R EF5 V L G = -------------------------------------------------------------------------------------Field strenght voltage [STEREO] Figure 19. Internal stereo blend characteristics
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The gain can be programmed through 4 bits in the "Stereo Decoder Adjustment"-byte. The MONO-voltage VMO (0dB channel separation) can be chosen selecting VSBL. All necessary internal reference voltages like REF5V are derived from a bandgap circuit. Therefore they have a temperature coefficient near zero. This is useful if the fieldstrength signal is also temperature compensated. But most of the IF-devices are applying a LEVEL-voltage with a TC of 3300ppm. The A673 offers this TC for the reference voltages, too. The TC is selectable with bit D7 of the "stereo decoder adjustment"-byte. Figure 20. Relation Between Internal and External LEVEL Voltages and Setup of Stereoblend
INTERNAL VOLTAGES REF 5V SETUP OF VST LEVEL INTERN REF 5V INTERNAL VOLTAGES SETUP OF VMO
LEVEL INTERN
LEVEL VSBL VSBL
58% 29%
VMO
VST
t FIELDSTRENGHT VOLTAGE
modAU639
VMO
VST
t FIELDSTRENGHT VOLTAGE
Highcut Control The highcut control set-up is similar to the stereoblend control set-up: the starting point VHCH can be set with 2 bits to be 42, 50, 58 or 66% of REF5V whereas the range can be set to be 17, 22, 28 or 33% of VHCH (see fig. 21). Figure 21. High cut characteristics
LOWPASS TIME CONSTANT
3*Deemp
Deemp
VHCL
D97AU640
VHCH
FIELDSTRENGHT
Functional Description of the Noise Blanker In the automotive environment spikes produced by the ignition and for example the wiper-motor disturb the MPX-signal. The aim of the noise blanker part is to cancel the audible influence of the spikes. Therefore the output of the stereo decoder is held at the actual voltage for a time between 22 and 38s (programmable). The block diagram of the noise blanker is given in fig.22
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Figure 22. Block diagram of the noise blanker
RECTIFIER RECT
MPX
+ VTH
MONOFLOP
HOLDN
+
PEAK LOWPASS MPOUT CONTROL +
THRESHOLD GENERATOR
ADDITIONAL THRESHOLD CONTROL
modAU856
In a first stage the spikes must be detected but to avoid a wrong triggering on high frequency (white) noise a complex trigger control is implemented. Behind the trigger stage a pulse former generates the "blanking"-pulse. An own biasing circuit supplies the noise blanker in order to avoid any cross talk to the signal path. Trigger Path The incoming MPX signal is high pass filtered, amplified and rectified. This second order high pass filter has a corner-frequency of 140kHz. The rectified signal, RECT, is low pass filtered to generate a signal called PEAK. Also noise with a frequency 140kHz increases the PEAK voltage. The resulting voltage can be adjusted by use of the noise rectifier discharge current. The PEAK voltage is fed to a threshold generator, which adds to the PEAK-voltage a DC-dependent threshold VTH. Both signals, RECT and PEAK+VTH are fed to a comparator, which triggers a re-triggerable monoflop. The monoflop's output activates the sample-and-hold circuits in the signal path for the selected duration. Automatic Noise Controlled Threshold Adjustment (ATC) There are mainly two independent possibilities for programming the trigger threshold: 1. the low threshold in 8 steps (bits D 0 to D2 of the noise blanker byte) 2. and the noise adjusted threshold in 4 steps (bits D3 and D4 of the noise blanker-byte, see fig. 15). The low threshold is active in combination with a good MPX signal without any noise; the PEAK voltage is less than 1V. The sensitivity in this operation is high. If the MPX signal is noisy (low fieldstrength) the PEAK voltage increases due to the higher noise, which is also rectified. With increasing of the PEAK voltage the trigger threshold increases, too. This particular gain is programmable in 4 steps (see fig. 17).
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ADDITIONAL THRESHOLD CONTROL MECHANISM Automatic Threshold Control by the Stereoblend voltage Besides the noise controlled threshold adjustment there is an additional possibility for influencing the trigger threshold. It is depending on the stereoblend control. The point where the MPX signal starts to become noisy is fixed by the RF part. Therefore also the starting point of the normal noise-controlled trigger adjustment is fixed (fig. 17). In some cases the behavior of the noise blanker can be improved by increasing the threshold even in a region of higher fieldstrength. Sometimes a wrong triggering occurs for the MPX signal often shows distortion in this range, which can be avoided even if using a low threshold. Because of the overlap of this range and the range of the stereo/ mono transition it can be controlled by stereoblend. This threshold increase is programmable in 3 steps or switched off with bits D0 and D1 of the fieldstrength control-byte. Over Deviation Detector If the system is tuned to stations with a high deviation the noise blanker can trigger on the higher frequencies of the modulation. To avoid this wrong behavior, which causes noise in the output signal, the noise blanker offers a deviation-dependent threshold adjustment. By rectifying the MPX signal a further signal representing the actual deviation is obtained. It is used to increase the PEAK voltage. Offset and gain of this circuit are programmable in 3 steps with the bits D6 and D7 of the stereo decoder-byte (the first step turns off the detector, see fig. 16). Multipath-Level To react on high repetitive spikes caused by a Multipath-situation, the discharge-time of the PEAK voltage can be decreased depending on the voltage-level at Pin MPout. There are two ways to do this. One way is to switch on the linear influence of the Multipath-Level on the PEAK-signal (D7 of field strength control byte). In this case the discharge slew rate is 1V/ms1. The second possibility is to activate a function, which switches to the 18k discharge if the Multipath-Level is below 2.5V (D7 of High-Cut-Control-Byte).
1
The slew rate is measured with RDischarge = infinite and VMPout = 2.5V
Functional Description of the Multipath-Detector Using the internal Multipath-Detector the audible effects of a multipath condition can be minimized. A multipath-condition is detected by rectifying the 19kHz spectrum in the fieldstrength signal. An external capacitor is used to define the attack- and decay-times (see block diagram, fig. 23). The MP_OUT-pin is used as detector-output connected to a capacitor of about 47nF and additionally the MP_IN-pin is selected to be the fieldstrength input. Using this configuration an external adaptation to the user's requirement is possible without affecting the "normal" fieldstrength input (LEVEL) for the stereo decoder. This application is given in fig. 29. To keep the old value of the Multipath Detector during an AF-jump, the MP-Hold switch can disconnect the external capacitor. This switch is controlled directly by the AFS-Pin. Selecting the "internal influence" in the configuration byte the channel separation is automatically reduced during a multipath condition according to the voltage appearing at the MP_OUT-pin. A possible application is shown in fig. 29.
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Figure 23. Block Diagram of Multi path Detector
Programming To obtain a good multipath performance an adaptation is necessary. Therefore the gain of the 19kHzbandpass is programmable in four steps as well as the rectifier gain. The attack- and decay-times can be set by the external capacitor value. Quality Detector The A673 offers a quality detector output, which gives a voltage representing the FM-reception conditions. To calculate this voltage the MPX-noise and the multipath-detector output are summed according to the following formula: VQual = 1.6 (VNoise-0.8 V)+ a (REF5V-VMpout). The noise-signal is the PEAK-signal without additional influences (see noise blanker description). The factor 'a' can by programmed from 0.6 to 1.05. The output is a low impedance output able to drive external circuitry as well as simply fed to an AD-converter for RDS applications. AF Search Control The TDA7411 is supplied with several functionality to support AF-checks using the stereo decoder. As mentioned already before the high impedance mute feature avoids any clicks during the jump condition. It is possible at the same time to evaluate the noise- and multipath-content of the alternate frequency by using the Quality detector output. Therefore the multipath-detector is switched automatically to a small time-constant. One additional pin (AFS) is implemented in order to separate the audio processor-mute and stereo decoder AF-functions. In Figure 24 the block diagram and control-functions of the complete AFS-functionality is shown (please not the pins FAS and SM are active low as well as all control-bits indicated by an over bar).
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Figure 24. Mute Control Logic
Test Mode During the test mode which can be activated by setting bit D0 of the testing-byte and bit D5 of the sub address byte to "1" several internal signals are available at the CDR pin. During this mode the input resistance of 100kOhm is disconnected from the pin. The internal signals available are shown in the data byte specification.
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I2C BUS INTERFACE DESCRIPTION Interface Protocol The interface protocol comprises: -a start condition (S) -a chip address byte (the LSB bit determines read / write transmission) -a subaddress byte -a sequence of data (N-bytes + acknowledge) -a stop condition (P)
CHIP ADDRESS MSB S 1 0 0 0 1 1 LSB 0 R/W ACK MSB A4 AZ T I SUBADDRESS LSB A3 A2 A1 A0 ACK MSB DATA DATA 1 to DATA n LSB ACK P
D03AU1526
S = Start ACK = Acknowledge AZ = AutoZero-Remain T = Testing I = Autoincrement P = Stop MAX CLOCK SPEED 500kbits/s Auto increment If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled. TRANSMITTED DATA (send mode)
MSB X X X X ST SM X LSB X
SM = Soft mute activated ST = Stereo X = Not Used The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chip address. Reset Condition A power on reset is invoked if the supply voltage is below than 3.5V. After that the following data are written automatically into the registers of all sub addresses:
MSB 1 1 1 1 1 1 1 LSB 0
The programming after POR is marked bold face / underlined in the programming tables. With that programming all the outputs are muted to Vref.
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TDA7411
SUBADDRESS (receive mode)
MSB I3 I2 0 1 I1 I0 A3 A2 A1 LSB FUNCTION A0 Auto Zero Remain 2 off on 0 1 Test Mode 3 off on 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Auto Increment Mode 4 off on Input Selector (main) Volume Treble Bass Speaker Attenuator Left Front Speaker Attenuator Right Front Speaker Attenuator Left Rear Speaker Attenuator Right Rear Soft Mute / Bass Programming Stereo Decoder Noise Blanker High Cut Control Field Strength. & Quality Configuration EEPROM Testing New Quality / Control Middle Filter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Byte (dec)
New implemented sub addresses 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 Input Selector (sub) Speaker Attenuator Left Free Speaker Attenuator Right Free Configuration Front Configuration Rear Configuration Free Mute 18 19 20 21 22 23 24
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DATA BYTE SPECIFICATION The status after Power-On-Reset is marked bold face / underlined in the programming tables. Input Selector (0)
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 : 1 1 0 1 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 FUNCTION Source Selector CDCH AUX CD MD/phone NV Acin0 AM FM In-Gain 15dB 14dB : 1 dB 0 dB CDCH Input Configuration quasi differential full differential
Volume and Speaker Attenuation (1, 4, 5, 6, 7, 19, 20)
MSB D7 1 : 1 0 0 0 : 0 0 : 0 0 X D6 0 : 0 0 0 0 : 0 0 : 1 1 1 D5 0 : 0 0 0 0 : 0 0 : 0 0 1 D4 0 : 0 0 0 0 : 0 1 : 0 0 X D3 1 : 0 0 0 0 : 1 0 : 1 1 X D2 1 : 0 0 0 0 : 1 0 : 1 1 X D1 1 : 0 0 0 0 : 1 0 : 1 1 X LSB D0 1 : 1 0 0 1 : 1 0 : 0 1 X +15dB : +1dB 0dB 0dB -1dB : -15dB -16dB : -78dB -79dB Mute FUNCTION
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Treble Filter (2)
MSB D7 D6 D5 D4 D3 0 0 : 1 1 0 1 0 0 1 1 1 0 1 0 1 D2 0 0 : 1 1 D1 0 0 : 1 1 LSB D0 0 1 : 0 1 Treble Steps 15dB 14dB : 1 dB 0 dB Boost / Cut Cut Boost Treble Center-frequency 10.0 kHz 12.5 kHz 15.0 kHz 17.5 kHz unused must be "1" FUNCTION
Bass Filter (3)
MSB D7 D6 D5 D4 D3 0 0 : 1 1 0 1 0 0 1 1 0 1 0 1 0 1 D2 0 0 : 1 1 D1 0 0 : 1 1 LSB D0 0 1 : 0 1 Bass Steps 15dB 14dB : 1 dB 0 dB Boost / Cut Cut Boost Bass Quality Factor 1.00 1.25 1.50 2.00 DC Mode Off On FUNCTION
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TDA7411
Speaker Attenuators (4-7) Please refer to Volume Programming. Soft Mute and Bass Programming (8)
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 0 0 0 1 1 1 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 Not used Must be "0" Mute Time Mute Time = 0.24ms Mute Time = 0.48ms Mute Time = 10.1ms Mute Time = 20.2ms Not used Must be "1" Bass Center-Frequency 60 Hz 70 Hz 80 Hz 100 Hz 150 Hz (if Q =2) Noise Blanker Time 38s 25.5s 32s 22s FUNCTION
Stereo Decoder (9)
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 STD Unmuted STD Muted IN-Gain IN-Gain IN-Gain IN-Gain 11 dB 8.5 dB 6 dB 3.5 dB FUNCTION
Stereo Decoder Off On Forced MONO MONO/STEREO switch automatically Noise Blanker PEAK charge current low Noise Blanker PEAK charge current high Pilot Threshold HIGH Pilot Threshold LOW Deemphasis 50s Deemphasis 75s
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Noise Blanker (10)
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 FUNCTION Low Threshold 65mV Low Threshold 60mV Low Threshold 55mV Low Threshold 50mV Low Threshold 45mV Low Threshold 40mV Low Threshold 35mV Low Threshold 30mV Noise Controlled Threshold 320mV Noise Controlled Threshold 260mV Noise Controlled Threshold 200mV Noise Controlled Threshold 140mV Noise Blanker OFF Noise Blanker ON Over Deviation Over Deviation Over Deviation Over Deviation Adjust 2.8V Adjust 2.0V Adjust 1.2V Detector OFF
High-Cut (11)
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 High-Cut OFF High-Cut ON max. High-Cut max. High-Cut max. High-Cut max. High-Cut VHCH at VHCH at VHCH at VHCH at VHCL at VHCL at VHCL at VHCL at 42% 50% 58% 66% 2dB 5dB 7dB 10dB REF5V REF5V REF5V REF5V FUNCTION
16.7% VHCH 22.2% VHCH 27.8% VHCH 33.3% VHCH
Strong Multipath Influence on PEAK 18k Off On (18k discharge if VMPout< 2.5V)
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TDA7411
Field Strength Control (12)
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 VSBL at VSBL at VSBL at VSBL at VSBL at VSBL at VSBL at VSBL at 29% 33% 38% 42% 46% 50% 54% 58% FUNCTION REF5V REF5V REF5V REF5V REF5V REF5V REF5V REF5V Adjust 2.3V Adjust 1.8V Adjust 1.3V Adjust OFF
Noise Blanker Field Strength Noise Blanker Field Strength Noise Blanker Field Strength Noise Blanker Field Strength Quality Quality Quality Quality
Detector Coefficient a=0.6 Detector Coefficient a=0.75 Detector Coefficient a=0.9 Detector Coefficient a=1.05
Multipath Influence on PEAK Discharge Off -1 V/ms
Configuration (13)
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 LSB D0 0 1 0 1 FUNCTION Noise Rectifier Discharge Resistor R = infinite RDC = 56k RDC = 33k RDC = 18k Multipath Detector Band pass Gain 6dB 12dB 16dB 18dB Multipath Detector internal influence ON OFF Multipath Detector Charge Current 0.2A 0.4A Multipath Detector Rectifier Gain Gain = 7.6dB Gain = 4.6dB Gain = 0dB Disabled
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Stereo Decoder Adjustment (14)
MSB D7 0 0 0 : 0 : 0 1 1 1 : 1 : 1 0 0 0 : 1 0 0 0 : 1 0 0 1 : 1 0 1 0 : 1 D6 D5 D4 D3 D2 0 0 0 : 1 : 1 0 0 0 : 1 : 1 D1 0 0 1 : 0 : 1 0 0 1 : 0 : 1 LSB D0 0 1 0 : 0 : 1 0 1 0 : 0 : 1 FUNCTION Roll-Off Compensation Not allowed 7.2% 9.4% : 13.7% : 20.2% Not allowed 19.6% 21.5% : 25.3% : 31.0% LEVEL Gain 0dB 0.66dB 1.33dB : 10dB
Testing (15)
MSB D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 LSB D0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION default value, see note Stereo Decoder Test Signals OFF Test Signals enabled if bit D5 of the sub address (test mode-bit) is set to "1", too External Clock Internal Clock Test Signals at CDR VHCCH Level intern Pilot magnitude VCOCON; VCO Control Voltage Pilot threshold HOLDN NB threshold F228 VHCCL VSBL Not used Not used PEAK Not used REF5V Not used VCO OFF ON Audio Processor Test Mode Enabled if bit D5 of the sub address (test mode-bit) is set to "1", too OFF
Note: This byte is used for testing or evaluation purposes only and must not set to other values than the default "11111110" in the application!
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New Quality / Control (16)
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION Reference Generation Internal Reference-Divider External Reference Force Quality Noise-Gain 15 dB 12 dB 9 dB 6 dB SC-Clock-Mode Fast Mode Normal Mode AutoZero Off On Smoothing Filter On Off Enable AF-Pin Enable Pin Disable Pin AF-Pin ST-Decoder-Mute-Influence On Off
Middle Filter (17)
MSB D7 D6 D5 D4 0 0 : 0 0 1 1 : 1 1 0 0 1 1 0 1 0 1 0 1 D3 0 0 : 1 1 1 1 : 0 0 D2 0 0 : 1 1 1 1 : 0 0 D1 0 0 : 1 1 1 1 : 0 0 LSB D0 0 1 : 0 1 1 0 : 1 0 Attenuation -15dB -14dB : -1 dB 0 dB 0 dB +1 dB : +14 dB +15dB Middle Center-frequency 500 Hz 1.0 kHz 1.5 kHz 2.0 kHz Mid Q Factor 1.0 2.0 FUNCTION
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Input Selector Sub (18)
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 1 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 FUNCTION Source Selector CDCH AUX CD MD/phone NV Acin0 AM FM Unused Must be "1" MD Input Mode Phone MD
Configuration Front Speaker (21)
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 FUNCTION Source Selector Middle filter output Bass filter output NV Phone ACin0 ACin1 ACin2 ACin3 Interrupt Left Interrupt No interrupt Interrupt Right Interrupt No interrupt Interrupt Source Left Phone NV Interrupt Source Right Phone NV Not used Must be "1"
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Configuration Rear Speaker (22)
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 FUNCTION
D7
D6
D5
D4
D3
D2
0 0 0 0 1 1 1 1
D1
0 0 1 1 0 0 1 1
D0
0 1 0 1 0 1 0 1 Source Selector Middle filter output Bass filter output NV Phone ACin0 ACin1 ACin2 ACin3 ACin1 Input Resistor Not allowed (50k) 50k 40k 30k Unused Must be "1"
0 0 1 1 1 1 1
0 1 0 1
Configuration Rear Speaker (23)
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 FUNCTION Source Selector Middle filter output Bass filter output NV Phone ACin1 ACin2 ACin3 ACin3_lowpass Unused Must be "1" Low Pass Corner Frequency flat 50 Hz 60 Hz 80 Hz 100 Hz 120 Hz not allowed (120 Hz) not allowed (120 Hz)
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Mute Configuration (24)
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION Front Left Speaker Muted Unmuted Front Right Speaker Muted Unmuted Rear Speaker Muted Unmuted Smoothing Bass off on Free Speaker Muted Unmuted Smoothing Low Pass off on Main Channel Muted Unmuted Sub Channel Muted Unmuted
APPLICATION CIRCUIT Figure 25. Standard Application
TDA7411
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mm DIM. MIN. A A1 A2 B C D D1 D3 E E1 E3 e L L1 k 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 12.00 10.00 8.00 0.80 0.60 1.00 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.004 0.464 0.386 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.015 0.057 0.018 0.008 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.024 0.039 0.030 0.480 0.401 0.480 0.401
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10 x 1.4mm)
0(min.), 3.5(typ.), 7(max.)
D D1 A A2 A1
33 34 23 22
0.10mm .004 Seating Plane
E1
B
44 1 11
12
E
B
C
e
L
K
TQFP4410
0076922 D
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TDA7411
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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